1. Field of the Invention
This invention relates to a method of fabricating a flash memory, and more particularly to a method of fabricating a split gate structure of a flash memory.
2. Description of Related Art
A nonvolatile memory is currently applied in electric devices such as for storing structure data, program data and other data needed to be repeatedly read and written. Within the catalog of a programmable nonvolatile memory, an erasable programmable read-only memory (EPROM) and an electrically erasable programmable read-only memory (EEPROM) are now of the highest interest. Generally, one flash memory includes two gates, wherein a floating gate made of polysilicon is for charge storing and a control gate for controlling data access. The floating gate is posited beneath the control gate and is usually at the status of "floating", without being coupled to any wiring lines. The control gate is coupled to a word line.
The flash memory technology is becoming technology of choice among other memory technologies, due to its capability to replace magnetic disk media. Split-gate source-side injection cell has very high programming efficiency and very low write currents. The key elements of the high injection efficiency cell consist of a weakly-on and a highly-on region along the conduction channel. Large potential drop across the narrow region near the source side of floating gate creates a large sum of hot-electrons. Mostly, the split-gate source-side injection cells suffer from the high resistance problems associated with the narrowly formed below-feature-size "sidewall-like" select gate or exhibit over-erase problems.
Recently, to overcome the over-erase problem, a high density triple poly split-gate source-side-injection cell is disclosed in "A novel high density contactless flash memory array using split-gate source-side injection cell foe 5V-only applications" in Symposium on VLSI Technology, 1994 by Y. Ma et al. Referring to FIG. 1, a flash memory cell is on a p-type substrate 10, having tunnel oxide 11, a floating gate 12 and a control gate 13, both of which are made of polysilicon. The floating gate 12 is formed beneath the control gate 13. After the formation of both of the floating gate 12 and the control gate 13, impurities are implanted into the substrate 10 to form the source/drain regions 14, 15. Then, a polysilicon layer is further formed above to form a select gate 16.
The select-gate controls the weakly-on region during programming and prevents unselected cells from conduction in program and read modes. The select-gate runs along the channel direction. This eliminates the need of below-feature-size poly, reduces select-gate delay and improves the speed over the sidewall type select-gate cells. The use of a select-gate allows the cell to operate in depletion mode.
However, as shown in FIG. 1, the distance between the two separated gates is small because the two separated gates share a common source/drain. Consequently, as depositing the polysilicon layer for the selected gate, poor step coverage even a void may occur, which influences the conductive quality of the polysilicon layer. Moreover, different arrays of the selected gates have different levels, which tend to occur short circuit.